Ashika Ajai — Software Engineer

Experienced and skilled engineer with 7-year experience looking to leverage extensive experience and expertise in VLSI design verification to deliver innovative and high-quality solutions for driving the successful development of complex semiconductor products. My Skillsets are: Verification scope : SOC Verification IP Verification Formal Verification Verification approach : Functional coverage SVA - Assertions Verification Languages : C++ Verilog VHDL System Verilog Verification Methodology : UVM C-based tests Scripting languages : Perl Python Tool Expertise : VCS Verdi NCSim VC Formal Perforce JIRA IP/Protocol : Ethernet MAC Layer AMBA AXI AXI Lite Boundary scan MBIST FPGA

Stackforce AI infers this person is a VLSI Design Verification Engineer with expertise in semiconductor product development.

Location: Bengaluru, Karnataka, India

Experience: 8 yrs 6 mos