Vivek Gupta — Software Engineer

***Working in the high speed core group at Qualcomm ***Worked in the ASIC R&D team as product development engineer at Globalfoundries... ***Worked on APR and Signoff flows of High-Speed IO, MIPI as part of Mixed-Signal IP Solutions group as contractor at Intel, consisting of: -Automatic P&R of power gated, multi-supply designs using ICC at 10/ 14nm. -Signoff runs, viz., STA using PrimeTime, Layout Verification using IC Validator (ICV), IC Workbench, Calibre & Genoa, FEV using Conformal LEC, SPYGLASS and RV using RedHawk, etc. ***Worked on P&R and Signoff of power gated block level designs as contractor at PMC-SIERRA, consisting of: -Placement & Routing using AtopTech Aprisa at 28nm. -Signoff runs, STA using GoldTime, noise analysis using Encounter Timing System, LEC using Conformal, power analysis using Encounter power system and LVS/ DRC using Calibre. ***Worked on Mixed Analog Design of Sigma Delta ADC as student at IIITA, consisting of: -Analog Design of Sigma Delta Modulator using Cadence Virtuoso Platform at 180 nm node including simulation, layout design and LVS. -Digital design of Low Pass filter and decimator (CIC filter ) in verilog language using Cadence NCSim, RTL Compiler, Encounter (Velocity) at 180 nm upto GDS II, Synopsys DC, VCS, PT at 90 nm upto synthesis, STA and Mentor Graphics Leonardo Spectrum at 180 nm upto gate-level synthesis. -Analog-Mixed Design using Cadence Virtuoso platform exploiting schematic entry method of the methods for mixed signal design at 180 nm including AMS simulation and Sigma-Delta ADC parameter extraction using cadence toolboxes.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical and Mixed Signal Design.

Location: Delhi, India

Experience: 11 yrs