Nithin N

Software Engineer

Bengaluru, Karnataka, India9 yrs 10 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in RTL to GDSII physical design.
  • Proven leadership in high gate count design sign-off.
  • Specialized in performance and area optimization.
Stackforce AI infers this person is a Physical Design Engineer specializing in VLSI and semiconductor industries.

Contact

LinkedIn

Skills

Core Skills

Physical DesignSignoffLeadership

Other Skills

Chip topPartitionPNRVery-Large-Scale Integration (VLSI)Static Timing AnalysisVerilogLinuxTeamworkPhysical VerificationClock Tree SynthesisICC 2ICCFloorplanningDesign Rule Checking (DRC)Layout Versus Schematic (LVS)

Experience

9 yrs 10 mos
Total Experience
4 yrs 11 mos
Average Tenure
8 yrs
Current Experience

Mediatek

3 roles

Senior Staff Engineer

Promoted

Jun 2024 – Present · 1 yr 11 mos

  • Design Plan , Chip-Top APR to PV SIGNOFF.
Chip topPartitionPhysical DesignSignoff

Staff Engineer

Jul 2020 – Aug 2024 · 4 yrs 1 mo

  • Accomplished complex high gate count design sign-off with quality.
  • Trained & groomed team members for successful project completion.
LeadershipPNRSignoff

Physical Design Engineer

Apr 2018 – Jun 2020 · 2 yrs 2 mos

  • Handled high gate count blocks signoff.
  • As Vendor- Pozibility Technologies Pvt Ltd.
LeadershipSignoff

Alten calsoft labs

Engineer

Apr 2016 – Feb 2018 · 1 yr 10 mos

Leadership

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