Prakash Mehra — CTO
Experienced Physical design Engineer with a demonstrated history of working in the Semiconductors industry in various technology nodes (18A, 3nm, 4nm, 7nm , 10nm , 55nm ). Skilled in Synthesis ,PnR ,Custom CTS, STA , Power(PTPX) , ECO , PV, LEC , EM-IR Fix , Perl , TCL , Strategic Planning, and Verilog Coding. Strong arts and design professional with a Bachelor of Technology focused in Electronics and Communications Engineering from B I T SINDRI.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in physical design and power management.
Location: Bengaluru, Karnataka, India
Experience: 10 yrs 8 mos
Career Highlights
- Expertise in advanced semiconductor technology nodes.
- Proficient in physical design and static timing analysis.
- Strong background in scripting with Perl and TCL.
Work Experience
Intel Corporation
SOC Power Lead (1 yr 8 mos)
Wafer Space - An ACL Digital Company
Technical Lead (1 yr 11 mos)
Cerium Systems
Senior Physical Design Engineer (1 yr 9 mos)
Intel Corporation
Senior Physical Design Engineer (7 mos)
SeviTech Systems Pvt. Ltd.
Senior Physical Design Engineer (1 yr 4 mos)
AMD
Physical Design Engineer (6 mos)
Intel Corporation
Physical Design Engineer (8 mos)
Synapse Design Inc.
Project Enginner (Physical Design) (2 yrs 3 mos)
AMD
Physical Design Engineer (1 yr 1 mo)
Asilicon Design Pvt Ltd
Physical Design Engineer (1 yr 8 mos)
Education
Bachelor of Technology at BIT Sindri