Atish Dhoke

Software Engineer

Bengaluru, Karnataka, India8 yrs 8 mos experience

Highly Stable

Key Highlights

Expert in Verilog coding and scripting languages.
Strong background in physical design and STA processes.
Proven track record in automation and optimization projects.

Stackforce AI infers this person is a Semiconductor and Manufacturing expert with a focus on physical design and automation.

Contact

Skills

Core Skills

PrimetimeVerilogShell ScriptingPlc Programming

Other Skills

STA DSU and CPU flow setupconstraints cleanupECO generationtiming closureSTA flow setup for Multi voltage designSOC flat STA flow setuptiming collateralCustomized script for automationSTA flow setupC (Programming Language)TCL scriptingTweakerPython (Programming Language)C++Bash

About

"No one is good at everything , but If you want to good at something, You must be passionate and hardworking." I am passionate about making technology good to better and better to best. I am strategic, organized and self motivated person. I am expert at learning circuit diagram and troubleshooting of problems. I am always ready to get new knowledge. I am good at PLC programming with AC /DC drive programming. I am currently working as senior Engineer in Samsung Semiconductor in physical design (STA) team. I am very good in VERILOG Coding, scripting (bash, c-shell , python ), PrimeTime tool .

Experience

8 yrs 8 mos

Total Experience

3 yrs 2 mos

Average Tenure

2 yrs 4 mos

Current Experience

Nvidia

Senior ASIC Physical Design Engineer

Jan 2024 – Present · 2 yrs 4 mos · Bengaluru, Karnataka, India · Remote

Samsung electronics

3 roles

Associate Staff Engineer

Mar 2023 – Jan 2024 · 10 mos

 STA DSU and CPU flow setup, constraints cleanup, ECO generation, timing closure.
 STA flow setup for Multi voltage design (SMVA).
 SOC flat STA flow setup for multiple projects and providing timing collateral to customers.
 Customized script for automation and easy debugging
 Worked in 3nm,4nm and 5nm technologies.
 Timing closer in multi-voltage design with 2.4Ghz frequency.

STA DSU and CPU flow setupconstraints cleanupECO generationtiming closureSTA flow setup for Multi voltage designSOC flat STA flow setup+3

Senior Engineer

Jul 2021 – Mar 2023 · 1 yr 8 mos

CPU Team - PD/STA Engineer

C (Programming Language)Verilog

Student Intern

Feb 2021 – Jul 2021 · 5 mos

I worked in physical design/STA team.
1. Shell script to perform STA run on design for different modes and different operating condition
2. TCL script to get all information (like data path delay, Cells, Latency, skew, crosstalk nets etc.) of timing path by entering start and end points
3. Performing DMSA on design for fixing violation

Uttam galva steels ltd.

Shift Engineer

Jul 2014 – Dec 2017 · 3 yrs 5 mos · Khopoli, Raigad, Maharashtra

I worked in Electrical Maintenance department. I have experience of maintenance of 4Hi mill, Annealing, Gas plant, Tube Mill, CRS and CTL line. I did some Power saving project here using PLC programming. I did time optimisation project by increasing auromation using PLC Programming.