Jnana Phaneendra — Software Engineer

Experienced in Complete PnR flow (Synthesis, FloorPlan, Placement, Cts, & Routing) & FullChip Floorplanning Have Good knowledge on Statc Timing Analysis(STA) Responsible for complete closure of blocks from synthesis to GDS in Tsmc 5nm & 3nm technologies Worked on Low power designs with multiple voltages. Have idea on timing budgeting. Worked on Fullchip tasks like Pin planning, Feed through planning and Repeater insertion. Good at scripting languages like TCL, PERL & Unix. Technologies worked on: Tsmc 6nm, 5nm & Tsmc 3nm

Stackforce AI infers this person is a Physical Design Engineer with expertise in ASIC design for advanced semiconductor technologies.

Location: Hyderabad, Telangana, India

Experience: 4 yrs 5 mos