Sourabh Sharma — Software Engineer

DFT/SoC Test Engineer with strong experience in scan insertion, low-power DFT, and ATPG across advanced technology nodes (12nm to 2nm). Skilled in Tessent, FastScan, and TetraMAX for ATPG, coverage debug, and pattern generation, with hands-on expertise in SSN-based architectures, OCC, and IJTAG/PDL/ICL flows. Experienced in driving end-to-end DFT implementation—from RTL integration and LEC constraints to STA validation, timing closure, and GLS signoff. Proven ability to collaborate with PD/STA teams to resolve timing challenges and ensure robust, high-coverage test solutions for complex SoCs. Passionate about delivering scalable, high-quality DFT architectures for next-generation semiconductor designs.

Stackforce AI infers this person is a DFT Engineer specializing in semiconductor design and testing.

Location: Bangalore Urban, Karnataka, India

Experience: 9 yrs 6 mos