Surya Nallathambi

Director of Engineering

Singapore, Singapore, Singapore15 yrs 7 mos experience
Highly Stable

Key Highlights

  • 14 years of expertise in VLSI Chip design and verification.
  • Proficient in UVM methodology and various hardware programming languages.
  • Strong analytical skills with a focus on committed results.
Stackforce AI infers this person is a VLSI Design and Verification Expert specializing in ASIC and SoC technologies.

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Skills

Core Skills

VlsiUvm MethodologyAsic

Other Skills

CPerlPythonShell scriptingLinuxOOPS ConceptsVerilogSystem VerilogSpecman-e LanguageUVM methodologiesSpecman CodingTestbench creationStimulus generationOVM Concepts HandlingUnix

About

PROFESSIONAL STATEMENT To build a career in an organization that will utilize my knowledge, creativity and skills in the field of VLSI Chip design and verification, and show excellence along with the organization. PROFILE Highly skilled versatile RTL Design Verification professional with 14 yearsof experience specializing in IP and SoC verification using ConstrainedRandom and Metric Driven verification with UVM methodology.Demonstrated expertise in debugging, analytical thinking and deliveringcommitted results. Proficient in various hardware programming languageslike system verilog and scripting with a solid understanding ofNetworking, Mobile/Modem SoC, Memory devices and server domains. Skills: System Verilog, Verilog, UVM Methodology and Perl scripting.

Experience

15 yrs 7 mos
Total Experience
3 yrs 6 mos
Average Tenure
1 yr 6 mos
Current Experience

Mediatek

Technical Manager

Nov 2024Present · 1 yr 6 mos · Singapore · On-site

Maxlinear

Senior Staff Digital IC Verification Engineer

Nov 2022Nov 2024 · 2 yrs · Singapore, Singapore · On-site

Intel corporation

Digital Design Engineer

Mar 2018Nov 2022 · 4 yrs 8 mos · Bengaluru Area, India · Hybrid

Sevitech systems

Senior Design Verification Engineer

Jan 2014Feb 2018 · 4 yrs 1 mo · Bangalore

  • Expertise in C, Perl, Python and Shell scripting, Linux, OOPS Concepts, Verilog, System Verilog, Specman-e Language and UVM methodologies.
  • Good understanding on ASIC Verification cycle, SoC Verification, UVM methodologies
CPerlPythonShell scriptingLinuxOOPS Concepts+6

Hcl technologies

ASIC DEVELOPER

Sep 2010Jan 2014 · 3 yrs 4 mos · CHENNAI

  • Verilog, Specman Coding, Testbench creation, Stimulus generation, OVM Concepts Handling, Perl and Shell Scripting. Unix work environment
VerilogSpecman CodingTestbench creationStimulus generationOVM Concepts HandlingPerl+4

Education

Birla Institute of Technology and Science, Pilani

M.Tech — Microelectronics

Jan 2019Jan 2021

Anna University Chennai

Bachelor of Engineering (B.E.)

Jan 2006Jan 2010

SRV Boys Higher Secondry School

Higher Secondry Education '+2'

Jan 2004Jan 2006

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