Jadhav Yogesh — Software Engineer
Experienced Verification Engineer with a demonstrated history of working in the semiconductor industry. Skilled in System Verilog, UVM, Verilog, Perl, C and C++. Strong quality assurance professional with a Master’s Degree with CGPA 8.09 from National Institute of Technology Warangal and currently working in Qualcomm.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in VLSI and Embedded Systems.
Location: Bengaluru, Karnataka, India
Experience: 9 yrs 3 mos
Skills
- Low Power Verification
- Systemverilog
- Embedded Systems
Career Highlights
- Expert in Low Power Verification and SystemVerilog.
- Strong background in semiconductor industry.
- Master's degree with high CGPA from a reputed institution.
Work Experience
Qualcomm
Staff Engineer (8 yrs 4 mos)
Eximius Design
Verification Engineer (5 mos)
Mindlance Technologies
Verification Engineer (5 mos)
RV VLSI
RTL Design & Verification Trainee(Front End) (6 mos)
CMC Limited,Delhi
Industrial Trainee (2 mos)
Education
Master’s Degree at National Institute of Technology Warangal
Bachelor’s Degree at University of Allahabad
Intermediate at Narayana Junior College, Hyderabad
High School at New Pragathi Vidyalayam High School
