Naadhan Kandasamy

Product Engineer

Bengaluru, Karnataka, India17 yrs 7 mos experience

Key Highlights

  • Expert in ASIC and VLSI design.
  • Led critical design tasks across multiple technology nodes.
  • Proven problem solver in complex engineering environments.
Stackforce AI infers this person is a semiconductor design expert specializing in ASIC and VLSI technologies.

Contact

LinkedIn

Skills

Core Skills

Signal IntegrityTiming ClosureProblem SolvingHigh Speed Interfaces

Other Skills

Layout Versus Schematic (LVS)Design Rule Checking (DRC)LeadVery-Large-Scale Integration (VLSI)Application-Specific Integrated Circuits (ASIC)TCLPhysical DesignVerilog

About

Accomplished Principle Design Engineer with extensive experience in the physical design and development of Application-Specific Integrated Circuits (ASICs), CPUs, and GPUs. Proven expertise in leading and executing critical tasks in Synthesis, Physical Design, Static Timing Analysis, IR/EM, LEC/CLP, Signal Integrity (SI), and Physical Verification across a diverse range of technology nodes, including 140nm, 90nm, 55nm, 40nm, 28nm, 22nm, 16nm, 7nm, 5nm, 3nm and 2nm. Highly skilled in driving innovative solutions within complex engineering environments. Holds a Bachelor of Engineering (B.E.) in Electronics and Communication from Kongu Engineering College, Anna University.

Experience

17 yrs 7 mos
Total Experience
2 yrs 7 mos
Average Tenure
8 mos
Current Experience

Cadence

Principle Design Engineer

Aug 2025 – Present · 8 mos · Bengaluru, Karnataka, India · Hybrid

Arm

Staff Engineer

May 2023 – Aug 2025 · 2 yrs 3 mos · Bengaluru, Karnataka, India

Apex semiconductor

Senior Staff Design Engineer

Feb 2021 – Apr 2023 · 2 yrs 2 mos · Bengaluru, Karnataka, India · Remote

Layout Versus Schematic (LVS)High Speed InterfacesSignal IntegrityProblem SolvingDesign Rule Checking (DRC)Timing Closure+1

Nxp semiconductors

Lead Design Engineer

Feb 2016 – Jan 2021 · 4 yrs 11 mos · Bangalore

Layout Versus Schematic (LVS)Signal IntegrityProblem SolvingDesign Rule Checking (DRC)Lead

Smartplay technologies

Lead Engineer

Oct 2014 – Feb 2016 · 1 yr 4 mos

Layout Versus Schematic (LVS)Signal IntegrityProblem SolvingDesign Rule Checking (DRC)Lead

Intel corporation

Contract Worker

Nov 2012 – Mar 2014 · 1 yr 4 mos · Embassy Building Kundanahalli Gate

  • Contract Worker for Intel. Worked on a 22nm node project.
Layout Versus Schematic (LVS)High Speed InterfacesSignal IntegrityProblem SolvingDesign Rule Checking (DRC)

Open silicon research pvt ltd

Senior ASIC DESIGN ENGINEER I

Jun 2011 – Sep 2014 · 3 yrs 3 mos · Bangalore

Layout Versus Schematic (LVS)Signal IntegrityProblem SolvingDesign Rule Checking (DRC)

Wipro technologies

Project Engineer

Jan 2008 – Jan 2011 · 3 yrs · Kochi, Kerala, India

Layout Versus Schematic (LVS)Signal IntegrityProblem SolvingDesign Rule Checking (DRC)Lead

Education

Kongu Engineering College under Anna University

B.E. — Electronics and Communication

Jan 2004 – Jan 2008

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