Surendra Tanakanti

Product Engineer

Bengaluru, Karnataka, India9 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

8+ years in Physical Design and Verification.
Expert in PNR flow and full chip signoff.
Hands-on experience with advanced technologies down to 4nm.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Verification.

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Skills

Core Skills

Physical DesignPnr

Other Skills

Floor planningPower routingPlacementCTSRoutingLVSDRCSystem on a Chip (SoC)SemiconductorsSTATiming ClosureICCLayout Versus Schematic (LVS)Design Rule Checking (DRC)TCL

About

1)Working as a Physical design / Physical verification Engineer in various projects of different technologies(4nm,5nm,10nm,14nm,28nm) with 8+ years of experience. 2)Expertise on PNR flow (Foorplanning & Power planning, Placement ,Cts, Routing) and Verification (DRC, LVS & Parasitic Extraction ). 3)Good understanding of LVS errors, Shorts, Opens, Soft check, Real and False errors. 4)Working exposer on analog routing and cleaning drc's in Full Chip Level . 5)Hands on exposer on block level , Section level PV closer and Skilled in using tools like IC Compiler, Caliber, Innovus. 6) Worked on Full chip Signoff drc and Pv clean up .

Experience

9 yrs 6 mos

Total Experience

1 yr 10 mos

Average Tenure

3 yrs 11 mos

Current Experience

Samsung semiconductor india

Associate Staff Engineer

Jun 2022 – Present · 3 yrs 11 mos · Banglore · Hybrid

Tessolve

Design Engineer

Jun 2021 – May 2022 · 11 mos · Banglore

Hcl technologies

Lead Engineer

Apr 2019 – Jun 2021 · 2 yrs 2 mos · Banglore

Intel corporation

Physical Design Engineer

Feb 2017 – Mar 2019 · 2 yrs 1 mo · Bengaluru, Karnataka, India

Rv-vlsi design center

Physical Design Engineer

Aug 2015 – Jan 2016 · 5 mos · Bangalore.

Profissional Experience as Physical Design Engineer, of Complex SOC’s using Synopsys ICC
Knowledge in PNR flow like Floor planning, Power routing, Placement ,Cts,Routing and Relability issues like Maintaining current densities (E M), Antenna effect, cross talk.
Worked on 14nm, 10nm SOC layout Verification flow.
Having Knowledge on , Signal Estimating width requirements of nets and its implementation and Shielding the nets.
Performed many ECO iterations to reach timing closure by Interfaced with front-end design team
Knowledge on concepts of LVS , DRC. Setup and Hold.

Physical DesignPNRFloor planningPower routingPlacementCTS+3