Vinay Kumar — Software Engineer
Worked on projects involving APHY using high speed SERDES protocols. Implemented RTL designing and Validation of 32T32R Macro RU. RTL designing the microarchitecture of Beamforming implementation for both Uplink and Downlink in 8T8R Macro RU. Hands on experience in ORAN protocols of 5G NR. Worked on AMBA protocols like AHB, APB, AXI, AXI lite interfaces, UART, SPI.
Stackforce AI infers this person is a skilled FPGA and RTL design engineer in the telecommunications industry.
Location: Bengaluru, Karnataka, India
Experience: 6 yrs 9 mos
Skills
- Fpga Design
- Rtl Design
Career Highlights
- Expert in RTL design and validation for advanced communication systems.
- Hands-on experience with 5G NR and ORAN protocols.
- Proficient in multiple FPGA design tools and methodologies.
Work Experience
Qualcomm
Senior Engineer (8 mos)
Intel Corporation
Sr. Logic Design Engineer (1 yr 2 mos)
Tejas Networks
FPGA Design Engineer (10 mos)
HFCL Limited
Senior R&D Engineer (2 yrs 1 mo)
Indian Institute of Technology, Delhi
Teacher Assistant (2 yrs)
Education
M.TECH at Indian Institute of Technology, Delhi
B.tech at Jaipur National University