Mihir Vaidya

Software Engineer

Austin, Texas, United States16 yrs 4 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Extensive experience in silicon design and verification.
  • Proficient in multiple programming languages and verification methodologies.
  • Strong background in embedded systems and ASIC design.
Stackforce AI infers this person is a semiconductor design and verification expert with a focus on embedded systems.

Contact

Skills

Core Skills

VerificationDesign Verification

Other Skills

UVMSystem VerilogFormal VerificationSystemCC/C++VCSSimvisionvManagerJasperOR1KARMPerlTCLOOPSC++

Experience

16 yrs 4 mos
Total Experience
1 yr 11 mos
Average Tenure
3 yrs 1 mo
Current Experience

Tesla

2 roles

Staff Silicon Design Engineer

Promoted

May 2025Present · 1 yr · Austin, Texas Metropolitan Area · On-site

Senior Design Verification Engineer

Apr 2023May 2025 · 2 yrs 1 mo · Austin, Texas Metropolitan Area · On-site

Apple

GPU Design Verification Engineer

Jul 2020Apr 2023 · 2 yrs 9 mos · Austin, Texas, United States

Broadcom inc.

4 roles

R&D IC Design Engineer 3

Jun 2019Jul 2020 · 1 yr 1 mo

R&D IC Design Engineer 3

Oct 2018May 2019 · 7 mos

R&D IC Design Engineer 2

Jun 2018Sep 2018 · 3 mos

R&D Engineer IC Design 2 at Broadcom Limited

Jun 2015May 2018 · 2 yrs 11 mos

  • Verify complex chips and IP cores, using skills and industry-standard tools such as System Verilog, UVM, C/C++, and Verilog,Computer Architecture
  • Define and implement functional test plans for specific subblocks/functions with SoC under development
  • Use coverage-driven test methodology to ensure comprehensive testing of the design
  • Ownership of Complex Bus Protocol UVC Models, including UVC development, BFM modelling & integration
  • Implementation of the Scoreboard and predictor chain for IP core
  • Implementation of the bench infrastructure for UVM test bench for IP core Verification
  • Owner of chip initialization sequence used by firmware team
  • Use of Formal Verification tools to exhaustively verify certain logic blocks within the design
  • CPU verification using directed and constrained random verification
  • C testbench infrastructure development for CPU verification
  • Development of C-Model (ISS) and Random Instruction Generator for CPU verification
  • Work with the design team to resolve any design/debug issues as they occur
  • Work with chip and IP teams for CPU integration
  • SoC verification for dual ARM core chip
  • EJTAG UVM UVC development and verification for chips
  • Skills:- UVM, System Verilog, Formal , SystemC, C/C++, VCS, Simvision, vManager, Jasper , OR1K , ARM, Perl, TCL, OOPS
UVMSystem VerilogFormal VerificationSystemCC/C++VCS+10

Worcester polytechnic institute

Teaching Assistant

Aug 2014May 2015 · 9 mos · Worcester Massachusetts

  • Responsible for performing teaching and teaching related duties to assist faculty
  • Teaching Assistant for the course on RF and Microwave Engineering and Introduction to Digital Design
  • Work closely in support with faculty to conduct labs, tutorials and teaching/help sessions
  • Proctors exams, grades tests and homework, and records grades in grade book
  • Assigns material in class as needed
  • Proctor and teach labs on Introduction to Digital Design in ISE
  • Conduct experiments for in class demos using Spectrum Analyzer, Oscilloscope and other RF instruments

Juniper networks

ASIC Engineering Intern

Jun 2014Aug 2014 · 2 mos · Westford Massachusetts

  • Designed the flow control for the Veloce Maximus Emulator to test large, complex high speed ASIC for Juniper's next generation products
  • Developed a C++ testbench to generate, process and analyze Ethernet traffic for the Veloce Maximus Emulator
  • Worked closely with verification engineers to run and debug regressions for Juniper's ASICs
  • Analyzed the UVM test environment
  • Tools and languages used and learnt- C++, Perl, TCL, Veloce Maximus Emulator, UVM, Verilog

Worcester polytechnic institute

Graduate Student Worker

Jan 2014May 2014 · 4 mos · Worcester

  • Development and maintenance of website using WordPress for the Department Chair

Office of dean of arts & science at worcester polytechnic institute

Office Assistant

Oct 2013May 2014 · 7 mos · Worcester, USA

  • Work 20 hours in a week
  • Job description-Performing a wide variety of responsible office support and administrative functions

Stupidsid

Part-Time Content Writer

Jun 2013Jun 2013 · 0 mo · Mumbai, India

  • Wrote solution set for the university question papers for the subject Wireless Networks

Gurukul india.com (ltd)

Part-Time Instructor

Dec 2012May 2013 · 5 mos · Thane, India

  • Taught Basic level Spanish language for 7 hours in a week

Central placement cell, f.c.r.i.t

Placement Co-ordinator

Aug 2012Apr 2013 · 8 mos · Navi Mumbai, India

  • Helped in the placement activities of the college

Stupidsid

Lecturer

Jul 2012Nov 2012 · 4 mos · Dadar

  • Taught the subject Basic Electrical and Electronics to first year engineering students as a part of StupidSid Learning Program.

Technophilia systems

Intern

May 2012May 2012 · 0 mo · Andheri(Mumbai)

  • Internship cum training program on Advance Robotics and Embedded C. Worked on AVR controllers, peripheral devices, protocols like USART, I2C, SPI, RS232 etc. Implemented projects using Image Processing.

Fr.c.r.i.t

Student

Jan 2009Jan 2013 · 4 yrs · Mumbai Area, India

  • Bachelors of Engineering in Electronics and Telecommunication Engineering

Education

Worcester Polytechnic Institute

Master’s Degree — Electrical and Computer Engineering

Jan 2013Jan 2015

University of Mumbai

Bachelor of Engineering (B.E.) — Electronics and Telecommunication

Jan 2009Jan 2013

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