Rishab Mukherjee

Software Engineer

Bengaluru, Karnataka, India7 yrs 10 mos experience

Key Highlights

Architected UVM-based testbenches achieving over 95% coverage.
Delivered first-silicon success for complex IPs with zero critical escapes.
Mentored junior engineers and contributed to technical conferences.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in IP and SoC verification.

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Skills

Core Skills

Functional VerificationIp VerificationUvmPre Silicon VerificationFunctional SafetyHardware Fault Analysis

Other Skills

SystemVerilogFunctional CoverageDebuggingComputer SimulationsObject-Oriented Programming (OOP)Computer ArchitectureProblem SolvingInterpersonal SkillsHardware EngineeringAPBHardware VerificationDVDigital DesignsTest PlanningAMBA AHB

About

Senior Pre-Silicon Verification Engineer with 6+ years of experience driving IP, Subsystem level verification across diverse domains including image processing, display, ethernet, and functional safety. Proven track record of architecting UVM-based testbenches from scratch, achieving over 95% + functional and code coverage, and mentoring junior engineers. Adept in critical test planning, functional coverage planning, assertions (SVA), DPI-C integration, RAL modeling, and verification flow automation. Recognized with multiple internal awards at Intel and Samsung for technical innovation and first-time success. Experienced in delivering first-silicon success for complex IPs with zero critical escapes. Actively contributes to technical conferences (DVCon, SWPC) and consistently aligns with best practices in verification closure, coverage analysis, and regression debug.

Experience

7 yrs 10 mos

Total Experience

2 yrs 5 mos

Average Tenure

7 mos

Current Experience

Amd

Senior Silicon Verification Engineer

Oct 2025 – Present · 7 mos · India · On-site

Intel corporation

4 roles

IP Design Verification Engineer

Nov 2023 – Oct 2025 · 1 yr 11 mos · On-site

Owning Pre Silicon Verification of Image Processing Unit's IO Die targeted for multiple SoCs
Coverage Analysis and Closure
IP Verification Sign Off
Supporting integration of IP in SoC environment
Developing small scale BFMs to verify targeted units

SystemVerilogFunctional CoverageFunctional VerificationIP Verification

Pre Silicon Verification/Validation Engineer

Promoted

Feb 2022 – May 2023 · 1 yr 3 mos

Pre Silicon Verification of different state of art IPs
Proficient with System Verilog coding
Involved in UVM testbench activities
Coverage Closure for IP signoff

DebuggingComputer SimulationsUVMIP Verification

Pre Silicon Systems Engineer

Jul 2019 – Feb 2022 · 2 yrs 7 mos

Pre Silicon Verification of generic and FuSa based IP.
Worked Under Pre Silicon Team under Internet of Things Group and involved in FPGA/HAPS based verification.
Worked under Library Automation Team and involved in Design Automation activities.

Computer SimulationsObject-Oriented Programming (OOP)Pre Silicon VerificationIP Verification

Undergraduate Technical Intern

Jul 2018 – Jul 2019 · 1 yr

Worked in Functional Safety Architecture Analysis Department under Internet of Things Group and vividly worked on hardware fault analysis and mitigation technologies in SoC .

Computer ArchitectureProblem SolvingFunctional SafetyHardware Fault Analysis