Saravanan S.

Product Engineer

Bengaluru, Karnataka, India16 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 18 years in semiconductor verification.
Expert in SystemC modeling and verification.
Received client appreciation for RapidIO integration.

Stackforce AI infers this person is a semiconductor verification expert with extensive experience in system-level design and validation.

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Skills

Core Skills

VerificationDdr IpLow Speed ProtocolsPcieEthernetMethodology DevelopmentSystemc

Other Skills

DDR5 IP VerificationScoreboard DevelopmentMemory EncryptionPLL Model EnhancementLow Speed PeripheralsUARTSPII2CData Transfer VerificationPMIC C++ Model VerificationPCIE-EP SOC VerificationTestbench ArchitectureProcessor ImplementationData Path VerificationAutomotive Ethernet

About

Career Overview: Experience: Over 18 years in semiconductor verification and SystemC modeling/Verification. Verification: 15+ years in IP/SOC verification from scratch, Also supported pre-silicon/post silicon validation. SystemC Modeling: 3+ years developing TLM PV/LT/AT Models. Also created Test and Verification Methodology (TVM) using SystemC, YouTube presentation on my work (https://www.youtube.com/watch?v=xp6da9RbKCk). Technical Expertise: Protocols: RapidIO, PCIe , USB, Networking Expertise : 1. Ethernet (802.3ch, 10G-BaseT, 10GBase-R, 1G-Base, MII/GMII/XGMII/XAUI/XGBR). Majorly worked on Ethernet Physical Layer 2. L4 (TCP/UDP/ICMP), L3 (IPv4/IPv6), 3. WIFI (802.11 a/b/g/e/n/ac/ah/ax) Memory Protocol Expertise : 1. DDR2/DDR3/DDR5 2. NOR/NAND/SPI-Flash, XSPI-JESD251 3. PSRAM/APSRAM Low speed protocols : SPI/I2C/UART/JTAG Processors: RISC-V, Ten silica, ARM Cortex-A9, MIPS, Micro blaze. Strong knowledge of RISC-V ISA. Methodologies: RVM, VMM, OVM, UVM, CRAVE, SCV randomization, TLM (1.0/2.0). Advanced UVM concepts like layered sequence. Lab Debug : Involved in pre/post-silicon validation. Involved in reproducing lab bugs in verification environment. Also worked on ARM's Virtual environment for creating testcase for post silicon validation.Received client appreciation (Hi-Silicon, China) for enabling RapidIO in SoC verification and FPGA bring-up.

Experience

16 yrs 9 mos

Total Experience

2 yrs 4 mos

Average Tenure

4 yrs

Current Experience

Amd

Senior Member Of Technical Staff (DDR IP Verification, Individual contributor)

Jun 2022 – Present · 3 yrs 11 mos · Bengaluru, Karnataka, India · Hybrid

Verification of DDR5 IP
● Owns the end to end scoreboard for both client and server variants.
● Owns Total Memory Encryption/Reg Model.
● PLL Model enhancement for client variants
● CLKIP <-> UMC verification for both server and client variants for different power management activity.

DDR5 IP VerificationScoreboard DevelopmentMemory EncryptionPLL Model EnhancementVerificationDDR IP

Sima.ai

Senior Verification Engineer (Individual contributor)

Feb 2021 – Jun 2022 · 1 yr 4 mos · Bengaluru, Karnataka, India · Remote

●Owned entire Low speed peripherals subsystem (UART(Tx/Rx)/SPI(Master/Slave)/I2C(Master/Slave)) and Data transfer paths between serial peripherals and memory via SDMA to OCM/DDR.
●verification of SPI in multiple modes (PROFILE-1.0) : standard, dual, quad, and octal.
● Porting test vectors (likely directed tests or stimulus) for Video Encoder/Decoder, from unit-level (block-level) simulation/environment to full SoC-level.

Low Speed PeripheralsUARTSPII2CData Transfer VerificationVerification+1

Western digital

Principal Engineer- Individual contributor

Nov 2020 – Feb 2021 · 3 mos · Bengaluru, Karnataka, India · Remote

Verification of PMIC C++ Model.

PMIC C++ Model VerificationVerification

Mobiveil inc.

Verification Architect

Nov 2019 – Aug 2020 · 9 mos · Chennai, Tamil Nadu, India · Remote

Verification of PCIE-EP SOC, used for validating AI-Chip.
● SOC consists of PCIE-EP/8-DDR/8-processor/OCM/UART/PSRAM/SPI.
● Architected entire testbench.
● Implemented processor which is executing c code and system verilog env handshaking.
● Data path verification of 8-Microblaze to UART/DDR/PCIE-EP/OCM.
● Datapath verification from PCIE-EP to DDR.
● Verification of inter processor communication between processors.
● Mentored 4 interns in the project.
● Supported LAB debug.

PCIE-EP SOC VerificationTestbench ArchitectureProcessor ImplementationData Path VerificationVerificationPCIE

Aquantia semiconductor india private limited

Senior Verification Engineer

May 2018 – Jul 2019 · 1 yr 2 mos · Bangalore Urban, Karnataka, India · On-site

● Architected and developed Automotive Ethernet (802.3ch) PCS VIP, using UVM Layered sequence
● Created RAL flow, using which is used by different blocks and subsystem

Automotive EthernetUVM Layered SequenceRAL Flow CreationVerificationEthernet

Test and verification solutions

Project Lead

Nov 2013 – Sep 2016 · 2 yrs 10 mos · Chennai, Tamil Nadu, India

1. Worked as consultant in Atheros-Qualcomm, Blu-Wireless-UK, Micron-UK
2. Architected TB and Verified RX-Offload-Engine for Wifi-11AX Chip supporting multi user. The testbench is scalable to any no. of users.
3. Created TVM Verification methodology using SystemC . Verified Instruction Set Unit of a co-processor using it. used CRAVE for randomization. Created functional covergare library using C++ which dumps result in OneSpin Format.
4. Wrote CSV parser in System Verilog, which parses PCIE transaction from PCIE Trace and generates PCIE transaction item, that will be feed to PCIE transactor. This is done to reproduce lab bug in verification environment
5. Managed team of 5 members

TB ArchitectureRX-Offload-Engine VerificationTVM MethodologySystemCVerificationMethodology Development

Gda technologies

Verification Engineer

May 2007 – Oct 2013 · 6 yrs 5 mos · Chennai, Tamil Nadu, India · On-site

● SystemC PV (Programmers View) modelling of UART/SPI/I2C/DDR/NOR flash controller. Also involved in post silicon validation
● Verification of RapidIO IP. Also involved in Pre-Silicon Validation of RapidIO IP, at customer location.
● Verification of Ethernet PHY (100M/1G/10G/MACSEC/XAUI/XGBR) ethernet PHY.
● Verification of USB HUB. Wrote the randomization layer, which captures lot of bug.
● Verification of 11-AC WIFI WMAC and RX-Offload engine(L2/L3/L4 protocol).
● Verification of NIC SOC with RDMA over ethernet using iWRAP and TCP offload engine feature.
● Verification of Solar Power Controller SOC

SystemC PV ModelingRapidIO IP VerificationEthernet PHY VerificationUSB HUB VerificationVerificationSystemC