Dec 2019 – Dec 2024 · 5 yrs · Bengaluru, Karnataka, India · Hybrid

• Worked as ASIC RTL design engineer.
• 1. Integration of Ethernet MAC for High Speed Serial IO subsystem. Interacting with Design Verification team to verify the functionality, running static QC checks like lint, CDC, Interacting with PD team for backend implementation and timing closure, are my primary responsibilities.
• 2. Micro-architecture, design and integration of debug blocks into SoC to facilitate functional debug during silicon bring-up.
• 3. Design and integration of debug TAP network for Imaging IP.
• 4. Insertion of Memory test (MBIST) logic for SoC using Mentor Tessent tool. Verified the MBIST logic using partition level and top level simulation. Delivered memory test patterns to ATE team.

Jun 2017 – Dec 2019 · 2 yrs 6 mos · Bengaluru, Karnataka, India · On-site

• 1. Worked on prototyping of SoC designs on custom FPGA platforms.
• 2. Modifying the ASIC RTL for FPGAs, FPGA synthesis, partitioning the design across multiple FPGAs, resolving timing issues if any, were some of my primary responsibilities.

Jan 2017 – Jun 2017 · 5 mos · Bengaluru, Karnataka, India · On-site

• Worked on digital design of control blocks for medical applications using Altera FPGAs

Jul 2010 – Jan 2017 · 6 yrs 6 mos · Bengaluru Area, India · On-site

• Worked as RTL design engineer with primary focus on implementation of digital signal processing operations on FPGA.
• 1. Involved in architecture and design of Digital Down Converter(DDC), pipelined FFT blocks.
• 2. Matlab/Scilab modeling of signal processing blocks.
• 3. Designed embedded processor system using Xilinx microblaze soft core processor, memory subsystem and serial I/O peripherals.
• 4. Designed data acquisition system from high speed parallel ADC.