Saurabh Pratap Gautam

Software Engineer

Bengaluru, Karnataka, India4 yrs 6 mos experience

Most Likely To Switch

Key Highlights

3 years of DFT engineering experience
Expert in scan insertion and ATPG methodologies
Passionate about optimizing semiconductor designs

Stackforce AI infers this person is a DFT Engineer specializing in semiconductor design and testing methodologies.

Contact

Skills

Core Skills

DftSimulation

Other Skills

Scan InsertionSSNSSN InsertionAutomatic Test Pattern Generation (ATPG)CADENCE VIRTUOSOLVDS technologyEDT

About

Hi, I'm Saurabh Pratap Gautam, a DFT (Design for Testability) Engineer with 3 years of experience specializing in scan insertion, ATPG (Automatic Test Pattern Generation), and Simulations. My passion lies in ensuring the seamless integration of DFT techniques into complex chip designs. I thrive on optimizing scan chains, implementing robust ATPG methodologies, and conducting comprehensive simulations to enhance test coverage and shorten test time. Looking ahead, I'm eager to continue my journey in DFT engineering, driving innovation and excellence in semiconductor design. Let's connect and explore opportunities to collaborate on exciting projects in the world of DFT and semiconductor engineering. Feel free to reach out! #DFT #Semiconductor #Engineering #ATPG #Scan_Insertion #Simulations

Experience

4 yrs 6 mos

Total Experience

1 yr 8 mos

Average Tenure

2 yrs 6 mos

Current Experience

Intel corporation

DFT Engineer

Jan 2024 – Jul 2024 · 6 mos · Bengaluru, Karnataka, India · On-site

Client Site

SSN InsertionSSNDFT

Cientra

DFT Engineer - I

Dec 2023 – Present · 2 yrs 5 mos · Bengaluru, Karnataka, India · On-site

Current Client - Intel, Role - DFT

Scan InsertionSSNDFT

Chipedge technologies pvt ltd

DFT - Trainee

Dec 2021 – Apr 2022 · 4 mos · Bengaluru, Karnataka, India

formal learning in association with synapse

DFT

Synapse design inc.

DFT Engineer

Sep 2021 – Oct 2023 · 2 yrs 1 mo · Bengaluru, Karnataka, India

Client site - SocioNext

Scan InsertionAutomatic Test Pattern Generation (ATPG)DFT

Indian institute of technology, guwahati

Summer Intern

May 2019 – Jul 2019 · 2 mos · Guwahati Area, India

Successfully completed the Project on High Speed Data Transmission LVDS technology and simulated the LVDS Circuit for 1Gbps, 2Gbps & 3Gbps Data Transmission rates on CADENCE VIRTUOSO using 0.18um CMOS Technology with the help of gdpk180, analogLib, ahdlLib etc Libraries.