Shashank Upreti

Software Engineer

Bengaluru, Karnataka, India14 yrs 10 mos experience

Highly Stable

Key Highlights

Over 11 years of VLSI Physical Design experience.
Led multiple complex designs from 90nm to 7nm technology nodes.
Expert in SOC Floorplanning and Physical Verification.

Stackforce AI infers this person is a VLSI Physical Design Engineer with expertise in complex SoC implementations.

Contact

Skills

Core Skills

Full Chip PlanningPhysical DesignTiming ClosureLogic Synthesis

Other Skills

FloorplanningDesign PlanningPhysical VerificationSTAPlace & RouteLayout Versus Schematic (LVS)Very-Large-Scale Integration (VLSI)System on a Chip (SoC)Design Engineering

About

Having 11 + years of experience in VLSI Physical Design. Worked on various projects on different technology nodes from 90nm to 7nm. Currently working as Full Chip Layout Implementation Lead, responsible for SOC Floorplanning, Synthesis, Pin Placement and integration for multi hierarchical, multi-million gate count big size server SOCs. Expertise in block-level implementation, taped out around 8+ complex designs across the different technology nodes in top-notch companies.Responsible for Synthesis & Netlist to GDSII, STA, and Physical Verification for partition/block/tile.

Experience

14 yrs 10 mos

Total Experience

4 yrs

Average Tenure

2 yrs 9 mos

Current Experience

Amd

SMTS Silicon Design Engineer

Sep 2023 – Present · 2 yrs 9 mos · Bengaluru, Karnataka, India · Hybrid

Intel corporation

SoC Design Engineer

Jul 2018 – Sep 2023 · 5 yrs 2 mos · Bengaluru, Karnataka, India · Hybrid

Responsible for Full Chip Floorplanning, design planning activities , partitioning, synthesis, pin placement, feasibility analysis.

FloorplanningPhysical DesignFull Chip PlanningDesign Planning

Qualcomm

Sr. Lead Engineer

Apr 2018 – Jul 2018 · 3 mos · Bengaluru, Karnataka, India · On-site

Responsible for Netlist to GDSII for a complex design of mobile SoC, mentoring couple of folks and helping in block closure.

Synapse design inc.

Sr. Physical Design Engineer

Feb 2015 – Apr 2018 · 3 yrs 2 mos · Bengaluru Area, India · On-site

Worked in Synapse Design as Sr. Physical Design Engineer for top-notch companies, on-site.
AMD, Bangalore
Responsible for floorplanning to GDSII, including STA and Physical Verification closure for a complex design in 7nm technology.
Mediatek, Bangalore
Responsible for floorplan to GDSII for congestion and timing critical large-size blocks in NOC Ethernet SoC projects.
Mentoring small team of junior members and helping them in design convergence.

FloorplanningPhysical DesignTiming ClosurePhysical Verification

Wipro technologies

Physical Design Engineer

May 2011 – Feb 2015 · 3 yrs 9 mos · Pune Area, India · On-site

Worked in Wipro Technologies for multiple customers (IMC Germany and China, Renesas Japan,Medtronics) in ODC projects in 90nm to 28 nm technology node, low power designs having different complexities.
Responsible for floorplan to GDSII , STA, Physical Verification, ECO of multiple blocks and full chip.

FloorplanningPlace & RouteLayout Versus Schematic (LVS)Logic SynthesisPhysical Design