VARSHA SINGH — Software Engineer

•Working on the NanoTime tool, collaborating closely with cross-functional Memory (IPG) teams on validation, debugging, and functionality enhancements. •Experienced in memory design where I worked with different compilers including register file (RF compiler) ,Synchronous (SRF compiler) and Single port SRAM across various technology nodes including 7nm, 8nm, 18nm and 22 nm. •My experience with the industry standard tools like Cadence Virtuoso and Solido has been integral to my work as a Design Engineer. •Performed compiler activities including characterisation, hierarchy updates in stimuli’s while porting from TSMC to Samsung. Implemented mixed vts design (LVT/RVT) for optimising timing and power consumption within RF compiler. • Write | Read stats using solido. • ADM (SNM)| Checked impacts of PVT |WRM | Iread | Leakage current | Understanding of memory architectures.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in memory architecture and validation.

Location: Bengaluru, Karnataka, India

Experience: 5 yrs 6 mos