Amit Pandey — Software Engineer

Core Expertise: CPU & GPU Timing Analysis, Timing Closure Experience: - Over 6 years at MediaTek. Key contributions to timing verification and closure for high-performance CPU and GPU subsystems within complex SoC architectures. - Experience with advanced nodes and multiple product generations. - Focus on ensuring critical paths meet timing requirements for both functionality and performance. Specializations: 1.Timing Constraints (SDC) Feedback:  Providing feedback on timing constraints, including DFT modes. 2. Critical Path & Violation Analysis: Analyzing critical paths and identifying timing violations. 3. Timing Signoff: Driving timing signoff using industry-standard tools like Synopsys PrimeTime & Tweaker. 4. ECO Implementation: Implementing Engineering Change Orders (ECOs) to resolve setup, hold, and DRV violations. 5. Power Analysis & Optimization (PTPX): Running and analyzing design power and implementing power ECOs for optimization. Work Environment & Approach: - Thrives in collaborative, fast-paced environments. - Focus on precision and performance. - Passionate about building efficient, timing-robust CPU/GPU blocks for next-generation mobile and consumer electronics.

Stackforce AI infers this person is a Semiconductor Engineering expert focused on CPU and GPU timing analysis.

Location: Bengaluru, Karnataka, India

Experience: 6 yrs 10 mos