Nasser Arif

Product Engineer

Bengaluru, Karnataka, India13 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 10 years of experience in AMS-CAD engineering.
Developed unified design system for timing flows.
Achieved significant runtime improvements through cloud-based solutions.

Stackforce AI infers this person is a Semiconductor Engineering expert with a focus on AMS methodologies and timing characterization.

Contact

Skills

Core Skills

Ams Simulation/verification FlowTiming Characterization Flow

Other Skills

ADEADEGXLADEXLAMS VerificationAMS designerASICAnalogApplication-Specific Integrated Circuits (ASIC)CMOSCadenceCadence AMS methodologyCadence SpectreCadence VirtuosoCollaborationDebugging

About

As an AMS-CAD Engineer at Intel Corporation with over 10 years of experience, I lead efforts to enhance timing characterization and AMS flow development, enabling efficient design processes for Intel's flagship products. My contributions include developing a unified design system for timing flows and deploying cloud-based solutions to achieve significant runtime improvements. Key Methodology Owned. AMS Simulation/Verification flow Timing Characterization flow

Experience

13 yrs 8 mos

Total Experience

4 yrs 6 mos

Average Tenure

7 yrs

Current Experience

Intel corporation

AMS-CAD Engineer

Jun 2019 – Present · 7 yrs · Banglore

Developed timing characterization flows for Analog/MS and custom standard cells, migrating to PrimeLib for improved accuracy and runtime.
Managed regression suite for high-quality solutions during flow updates, achieving 90% accuracy in resource estimation.
Collaborated with EDA vendors to drive key methodologies and achieve up to 4X runtime improvement in 2024.

AMS Simulation/Verification flowTiming Characterization flowMixed-Signal Integrated CircuitsEDACadence VirtuosoScripting+26

Invecas

Sr. AMS Verification/Methodology Engineer

Mar 2018 – Jun 2019 · 1 yr 3 mos · Bengaluru Area, India

Created robust AMS verification environment for Serdes IP 12/25GBPS on GF node.
Developed Verilog Models for leaf level cell and validated with schematics.
Collaborated with DV team to create testbenches for validating various scenarios.

Cadence design systems

2 roles

Senior Application Engineer

Promoted

Jul 2014 – Mar 2018 · 3 yrs 8 mos

Provided expert level support in Cadence AMS methodology for semiconductor companies, ensuring smooth project execution.
Delivered comprehensive training sessions on Cadence AMS methodology to enhance customer understanding and usage.
Collaborated closely with internal stakeholders on various projects to drive innovation and efficiency.