Vanaja Marapa Reddy

Software Engineer

India8 yrs 4 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in Functional Verification methodologies.
  • Proficient in Open Verification Methodology.
  • Strong background in SoC design verification.
Stackforce AI infers this person is a Design Verification Engineer specializing in semiconductor verification methodologies.

Contact

LinkedIn

Skills

Core Skills

Functional VerificationOpen Verification Methodology

Other Skills

Design Verification TestingVerilogSystem on a Chip (SoC)Universal Verification Methodology (UVM)SystemVerilog

Experience

8 yrs 4 mos
Total Experience
4 yrs 2 mos
Average Tenure
4 yrs 6 mos
Current Experience

Intel corporation

SoC Design Verification Engineer

Nov 2021 – Present · 4 yrs 6 mos · Bengaluru, Karnataka, India · On-site

Open Verification MethodologyFunctional Verification

Atria logic inc.

Verification Engineer

Nov 2017 – Sep 2021 · 3 yrs 10 mos · Bengaluru, Karnataka, India · On-site

Open Verification MethodologyFunctional Verification

Maven silicon

Trainee

Jun 2017 – Nov 2017 · 5 mos · Bengaluru, Karnataka, India

Education

MADANAPALLE INSTITUTE OF TECHNOLOGY & SCIENCE

Master of Technology - MTech — Vles

Aug 2015 – Apr 2017

GATES Institute of Technology, Gooty

Bachelor of Technology - BTech — Electronics and communication engineering

Aug 2011 – Apr 2015

Stackforce found 100+ more professionals with Functional Verification & Open Verification Methodology

Explore similar profiles based on matching skills and experience

Hemant Chawla

Hemant Chawla

Principal Protocol Solutions Engineer

at Synopsys Inc

New Delhi, India14 yrs 9 mos exp
PCIeTestingVerification
saurabh chhabra

saurabh chhabra

Senior Staff Manager

at Qualcomm

Noida, India20 yrs 9 mos exp
Test PlanningHigh Performance Computing (HPC)
Rakesh Singh

Rakesh Singh

Sr. Principal Solutions Engineer

at Cadence

Bengaluru, India13 yrs 11 mos exp
Vishal Mistry

Vishal Mistry

Technical Manager

at eInfochips (An Arrow Company)

Ahmedabad, India17 yrs 1 mo exp
Kamna Varshney

Kamna Varshney

Senior Principal Product Validation Engineer

at Cadence Design Systems

Delhi, India20 yrs exp
ASICEDA
Pranav Joshi

Pranav Joshi

Verification Lead/Architect

at Intel Corporation

Ahmedabad, India29 yrs 6 mos exp
System VerilogVIP developmentHVLSpecman
Ashwani Kumar

Ashwani Kumar

Staff Engineer

at Qualcomm

Bengaluru, India12 yrs 9 mos exp
Network on chip DesignVerification
Murugan A

Murugan A

Engineering Manager

at MediaTek

Bengaluru, India14 yrs 7 mos exp
VerificationPCIe