Ayush Renith

Software Engineer

Singapore, Singapore2 yrs 6 mos experience

Key Highlights

Expert in Verification Engineering with UVM.
Proven track record in performance testing improvements.
Skilled in RISC-V development and assembly programming.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in UVM and RISC-V.

Contact

Skills

Core Skills

Verification EngineeringUvmRisc-v Development

Other Skills

ACEAXIAXI4Adobe LightroomArduinoArduino IDEAssembly LanguageC (Programming Language)C++Cache CoherencyCache VerificationCinematographyCraftsmanshipDaVinci ResolveDebugging

Experience

Canaan inc.

Verification Engineer

Aug 2025 – Present · 7 mos · Singapore · On-site

Architected and developed a comprehensive test-plan for RAS verification for a 3DDRAM controller UVM testbench.
Developed a fully scalable system for performance testing - enabling easy test writing, execution and result tabulation for 1000+ test scenarios and improving performance by 20%.
Implemented an AXI4 interface monitor and backdoor memory checker that validates memory for all address overlaps and read/write ordering dependencies across all test scenarios.

AXIUniversal Verification Methodology (UVM)Memory ControllersCache CoherencyVerification EngineeringUVM

Sifive

2 roles

Verification Engineer

Aug 2022 – Jul 2024 · 1 yr 11 mos

Developed a unit-level UVM testbench for L3 cache verification, including bring-up, smoke test writing, and debugging fails.
Created a targeted yet scalable test-plan for cache flushing and locking features and managed it’s regressions and debug.
Designed and implemented scoreboard, monitor, and drivers for a scalable generic protocol unit-level testbench. Thus enabling plug-and-play testing and scoreboarding for 8+ modules and drastically improving coverage and project timelines.
Experienced in Tile-Link 1 & 2, ACE and AXI4 protocol inter-conversion, scoreboards, achieved coverage closure of >95% on 2 projects and reported and fixed 80+ bugs.

Universal Verification Methodology (UVM)Tile-LinkACEAXI4Verification EngineeringUVM

Intern

Feb 2022 – Aug 2022 · 6 mos

Developed an in-house Risc-V assembly test generator to generate random CPU tests.
Wrote scripts to parse and convert CPU memory concurrency tests from ARM Litmus to RISC-V assembly.
Worked on debugging of vector processor fails.

RISC-VAssembly LanguageScriptingRISC-V Development