Feb 2024 – Present · 2 yrs 1 mo

• VCS simulation performance

May 2017 – Feb 2024 · 6 yrs 9 mos

• Project: Low power(UPF) in FPGA based emulation & prototyping
• Description:
• Power intent of a SOC or IP is described in a separate TCL based language called UPF(Unified Power Intent). The intent of this project is to implement UPF intent in the SOC or IP & verify the design with respect to the correct design functioning when power sequencing of the design being performed by the user software on the design. While modelling the UPF logic, it requires to keep in mind that all UPF logic & design will be mapped to FPGA based 2-state emulator (called Zebu) or prototyping (called HAPS) hardware. The software stack should be high performance in compile time and run-time.
• Responsibilities:
• Designing an FPGA friendly software architecture which can cater to solve all required low power (UPF) features implementation. I have implemented a high-performance low power software stack along with leading the team to add new low power features to the tool.
• Core Technology Used: HDL Synthesis, technology(FPGA cell) mapping, FPGA routing(hmetis, auto clustering).
• Other tools & technique used: C/C++, multi-threading, HDL(Verilog/VHDL), UPF, tcl, Machine learning & AI

Jan 2009 – Feb 2017 · 8 yrs 1 mo

• Project: Low power(UPF) in VCS simulator Low Power
• Description:
• The purpose of this project was to support low power(UPF) natively with VCS simulation for following reasons:
• The ease of use with VCS
• The high runtime performance compare to reference simulation
• The high compile performance compare to reference simulation
• Ease of debug with VCS graphical , tcl & C/C++ interface
• Responsibilities:
• My role in this project was to write specification, design & architecting the flow including implementation. I also leading a team to add new feature to the simulator.
• Core Technology Used: compiled machine code generation
• Other tools & technique used: C/C++, distributed processing, HDL(Verilog/VHDL), UPF, tcl

May 2004 – May 2009 · 5 yrs

• Project: VCS Mixed HDL compile performance
• VHDL compile time has overhead of reading same VHDL file header repeatedly. The purpose of this optimization was to read dependency file only once & extract required information in single reading.
• Responsibilities:
• Implemented the optimization to provide compile time boost significantly.
• Project: VCS Checker
• The purpose of this project is to implement linting checks into VCS framework. As part of this project, it had hardware synthesis & hardware checks is written using inferred logic. Also a netlist view was created to write netlist checks.
• Hardware synthesis
• HDL Linting checks
• Netlist checks
• Netlist view creation
• Responsibilities:
• In these projects I was involved in writing specification & then implementing the specification in the tool.
• Project: Static HDL Linting checker(Leda)
• This is a standalone linting tool which had programmability with which user can write their own rule on HDL. The programmability was on user RTL using new language. This part of the tool is called block level checker. There was another feature in the tool which is called netlist checker. For this , user can provide netlist generated by DC & liberty DB & using netlist checker , one can select pre-written netlist checks or can write their own new netlist checks using TCL interface.
• Responsibilities:
• My role was to maintain and enhance block level checker.