Ranjith Maddi — Software Engineer
Digital Design, Micro-Architecture, RTL coding/Integration, Simulation, Timing closures FPGA design. Experience of working on many industry standard protocols and interfaces like SPI, I2C, knowledge on UART, AXI, Pcie. Complete design cycle for FPGA based systems including RTL coding/Integration, Verification and Synthesis and STA. Worked on Xilinx FPGAs, having basic knowledge of device architectures. Having knowledge on CDC design technique for FPGA design. Expertise in developing Designs with Verilog and good in VHDL programming. Have sound knowledge in FPGA/ASIC Design Flow. Worked with various tools – Xilinx ISE and VIVADO, ModelSim and QuestaSim. Worked on Xilinx Chip scope analyzer and ILA analyzer. Sportive team player, motivates the team members to excellence, understands the value and importance of delegating work and responsibilities. Strong communication, analytical, debugging and presentation skills.
Stackforce AI infers this person is a VLSI design engineer with expertise in FPGA and RTL development.
Location: Hyderabad, Telangana, India
Experience: 9 yrs 8 mos
Skills
- Fpga Design
- Rtl Design
Career Highlights
- Expert in FPGA design and RTL coding.
- Proficient in Verilog and VHDL programming.
- Strong team player with excellent communication skills.
Work Experience
AMD
Sr Design Application Engineer (5 yrs 9 mos)
Mobiveil Inc.
Engineer (2 yrs 1 mo)
eInfochips (An Arrow Company)
RTL Design Engineer (9 mos)
Trylogic Soft Solutions AP Pvt Ltd
VLSI designer (1 yr 1 mo)
Education
Master’s Degree at JNTUH
