Md Majid Ansari

Software Engineer

South Delhi, Delhi, India4 yrs 4 mos experience

Key Highlights

  • Expert in advanced VLSI memory layout design.
  • Hands-on experience with TSMC 2nm and 3nm technologies.
  • Proficient in DRC, LVS, and ECO implementation.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI memory layout and advanced technology nodes.

Contact

Skills

Core Skills

Memory Layout Design

Other Skills

FloorplanningDRCLVSECO implementationECOAntennasLayout Versus Schematic (LVS)ShieldingMATLABC++EnglishEngineeringPrinted Circuit Board (PCB) DesignSpreadsheetsMicrosoft Excel

About

I am a VLSI Memory Layout Design Engineer with hands-on experience across advanced technology nodes, including TSMC 2nm & 3nm and Intel 18A GAA-FET process technologies. Over the course of my career, I have worked extensively on SRAM compilers, leaf cell development, and layout quality checks, delivering robust and signoff-ready designs. My expertise includes: Memory Layout & Architecture: Strong understanding of memory functionality, signal flow, floor planning, and development of leaf cells (SACM, CMUX, GIOM, REBUFFER, etc.). Quality Analysis & Verification: Skilled in DRC, LVS, Ch-cell creation, density checks, VERC, EMIR, SPM, LOD fixes, antenna checks, and LEF validation. Advanced Node Experience: Hands-on with GAA, FinFET, and CMOS processes; strong knowledge of layout-dependent effects (Latch-Up, WPE, STI, LOD) and process-invariant techniques (Common Centroid, Interdigitized). Problem Solving & Optimization: Proficient in implementing ECOs, EMIR/power fixes, PowerXT, and layout-dependent effect mitigation. Tools & Automation: Experienced with Cadence Virtuoso and Synopsys Custom Compiler; scripting in Shell for automation and debugging. I take pride in debugging complex design issues, meeting project deadlines with quality, and contributing to team success by mentoring juniors. My project portfolio spans: TSMC 2nm: Developed SRAM compiler cells, performed DRC/LVS, EMIR fixes, CalQA improvements, PowerXT fixes. TSMC 3nm: Designed BSR wrapper, executed ECOs, EMIR fixes, instance-level checks. Intel 18A HS2PRF: Leaf cell & Ch-cell development, multi-PDK DRC validation. SS8_RA1HDP & IN22FF_HD2PRF: ECO implementation, LOD fixes, EMIR fixes, and comprehensive DRC/LVS. I am passionate about pushing technology scaling limits and ensuring robust, high-quality memory designs at cutting-edge nodes.

Experience

4 yrs 4 mos
Total Experience
2 yrs 8 mos
Average Tenure
2 mos
Current Experience

Samsung semiconductor

Associate Staff Engineer

Apr 2026Present · 2 mos · Bengaluru, Karnataka, India

Broadcom

Memory Layout Designer

Aug 2024Mar 2026 · 1 yr 7 mos · Bengaluru, Karnataka, India · On-site

Synopsys inc

Memory Layout Engineer

Apr 2022Jul 2024 · 2 yrs 3 mos · Noida, Uttar Pradesh, India

  • Technology Proficiency: Experience in designing full custom SRAM memory layouts for advanced technologies, including GAAFET and FINFET, across various nodes such as Intel 18A and SS8.
  • SRAM Memory Compilers: Specialized in creating layouts for various blocks within SRAM memory compilers.
  • Critical Block Design: Proficient in designing critical blocks.
  • Instance Level Checks: I perform instance-level checks like DRC, LVS, ERC, and EMIR to ensure design accuracy and reliability.
  • Release Phases: Successfully navigated through multiple release phases, including LEF release, test chip GDS release, and full compiler release.
  • ECO Implementation: Experienced in assessing feasibility and implementing Electrical Change Orders (ECO) in designs.
Memory layout designFloorplanning

Zia semiconductor pvt ltd

Design Engineer

Jan 2022Mar 2026 · 4 yrs 2 mos · Bengaluru, Karnataka, India

Memory layout designFloorplanning

Education

Jamia Millia Islamia

BTech - Bachelor of Technology — Electronics and Communications Engineering

Aug 2017Jul 2021

Woodbine Modern School, Darbhanga

Intermediate

Apr 2015Mar 2016

Woodbine Modern School, Darbhanga, Bihar

High School

Apr 2013Mar 2014

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