Md Majid Ansari — Software Engineer
I am a VLSI Memory Layout Design Engineer with hands-on experience across advanced technology nodes, including TSMC 2nm & 3nm and Intel 18A GAA-FET process technologies. Over the course of my career, I have worked extensively on SRAM compilers, leaf cell development, and layout quality checks, delivering robust and signoff-ready designs. My expertise includes: Memory Layout & Architecture: Strong understanding of memory functionality, signal flow, floor planning, and development of leaf cells (SACM, CMUX, GIOM, REBUFFER, etc.). Quality Analysis & Verification: Skilled in DRC, LVS, Ch-cell creation, density checks, VERC, EMIR, SPM, LOD fixes, antenna checks, and LEF validation. Advanced Node Experience: Hands-on with GAA, FinFET, and CMOS processes; strong knowledge of layout-dependent effects (Latch-Up, WPE, STI, LOD) and process-invariant techniques (Common Centroid, Interdigitized). Problem Solving & Optimization: Proficient in implementing ECOs, EMIR/power fixes, PowerXT, and layout-dependent effect mitigation. Tools & Automation: Experienced with Cadence Virtuoso and Synopsys Custom Compiler; scripting in Shell for automation and debugging. I take pride in debugging complex design issues, meeting project deadlines with quality, and contributing to team success by mentoring juniors. My project portfolio spans: TSMC 2nm: Developed SRAM compiler cells, performed DRC/LVS, EMIR fixes, CalQA improvements, PowerXT fixes. TSMC 3nm: Designed BSR wrapper, executed ECOs, EMIR fixes, instance-level checks. Intel 18A HS2PRF: Leaf cell & Ch-cell development, multi-PDK DRC validation. SS8_RA1HDP & IN22FF_HD2PRF: ECO implementation, LOD fixes, EMIR fixes, and comprehensive DRC/LVS. I am passionate about pushing technology scaling limits and ensuring robust, high-quality memory designs at cutting-edge nodes.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI memory layout and advanced technology nodes.
Location: South Delhi, Delhi, India
Experience: 4 yrs 4 mos
Skills
- Memory Layout Design
Career Highlights
- Expert in advanced VLSI memory layout design.
- Hands-on experience with TSMC 2nm and 3nm technologies.
- Proficient in DRC, LVS, and ECO implementation.
Work Experience
Samsung Semiconductor
Associate Staff Engineer (2 mos)
Broadcom
Memory Layout Designer (1 yr 7 mos)
Synopsys Inc
Memory Layout Engineer (2 yrs 3 mos)
Zia Semiconductor Pvt Ltd
Design Engineer (4 yrs 2 mos)
Education
BTech - Bachelor of Technology at Jamia Millia Islamia
Intermediate at Woodbine Modern School, Darbhanga
High School at Woodbine Modern School, Darbhanga, Bihar