Vismay Kansara — DevOps Engineer

I drive timing closure and signoff for high-performance SoCs — turning timing risk into delivery certainty. As an STA and Physical Design leader, I specialize in SoC-level timing convergence, quality signoff, and ECO-driven optimization for complex client and server chipsets. I’ve led multi-partition teams through full-chip signoff, balancing performance, power, and manufacturability across corners. My focus is on results — achieving clean signoff, ensuring robust timing, and mentoring engineers to deliver at scale. I bring a systematic approach to problem-solving and thrive in cross-functional environments, working closely with SD, DFx, clock, and physical design teams to drive timing closure end to end. Highlights • Published “Signoff Methodology for IPs/SS used as Hyperscale” – DTTC 2022 • Recognized for quality-driven tape-ins and consistent on-time delivery • Delivered multiple generations of server SoCs with robust timing and clean signoff • Mentored engineers and interns, fostering technical growth and leadership skills Core Strengths STA · Physical Design · SoC Integration · Timing Convergence · ECO Generation · Quality Signoff · Noise & DRV Closure · Cross-Functional Collaboration · Leadership & Mentorship If you’re building SoC teams that demand precision, reliability, and results — let’s connect: vismaykansara@gmail.com

Stackforce AI infers this person is a Semiconductor expert specializing in SoC design and timing closure.

Location: Bengaluru, Karnataka, India

Experience: 7 yrs 10 mos